Intel’s developer portal published a technical article on AADC’s approach to accelerating quantitative simulations. The article explains how AADC works at the hardware level: extracting the Directed Acyclic Graph (DAG) of mathematical operations from existing Python or C++ code, optimizing the graph, and JIT-compiling it to native machine code that fully exploits Intel Xeon processor features.
How AADC Leverages Intel Hardware
AADC’s JIT compiler targets AVX2 and AVX-512 instruction sets available on Intel Xeon processors. By compiling the extracted computation graph directly to SIMD instructions, AADC processes 4 (AVX2) or 8 (AVX-512) independent evaluations per clock cycle. The compiler also optimizes memory access patterns, register allocation, and instruction scheduling — optimizations that are impossible when running through the Python interpreter or even through hand-written C++ with standard compilers.
Key Technical Details
The article covers AADC’s three-phase workflow: recording (executing the model once with active types to capture the DAG), compilation (JIT-compiling the DAG to native code), and evaluation (replaying the compiled kernel with new inputs). It demonstrates this on financial Monte Carlo simulations where the same kernel is evaluated millions of times with different market scenarios.
Performance on Intel Xeon
Benchmark results on Intel Xeon Scalable processors show that AADC-compiled kernels achieve near-theoretical peak throughput for the underlying mathematical operations. The article provides concrete numbers for pricing and Greeks computation, demonstrating that the code generation approach consistently outperforms both interpreted Python and traditionally compiled C++.
Read the full article on Intel Developer
Published by MatLogica. Implemented using AADC, a commercial adjoint AD compiler (matlogica.com).